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INTEGRATED CIRCUITS
DATA SHEET
SAA4960 Integrated PAL comb filter
Preliminary specification File under Integrated Circuits, IC02 1996 Oct 15
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
FEATURES * One chip adaptive PAL comb filter * Time discrete but continuous amplitude signal processing with analog interfaces * Internal delay lines, filters, clock processing and signal switches * Alignment-free * No hanging dots or residual cross colour on vertical transients * Few external components. QUICK REFERENCE DATA SYMBOL VCCA VDDD VCCO VCCPLL ICCO IDDD ICCA ICCPLL V17(p-p) V10(p-p) V1(p-p) V14(p-p) V12(p-p) V15(p-p) analog supply voltage digital supply voltage analog supply voltage output buffer analog supply voltage PLL analog supply current output buffer digital supply current analog supply current analog supply current PLL CVBS and Y input signal (peak-to-peak value) chrominance input signal (peak-to-peak value) subcarrier input signal (peak-to-peak value) luminance output signal (peak-to-peak value) chrominance output signal (peak-to-peak value) CVBS and Y output signal (peak-to-peak value) PARAMETER MIN. 4.75 4.75 4.75 4.75 - - - - 0.7 - 100 0.6 - 0.6 5 5 5 5 70 10 35 1.5 1 0.7 200 1 0.7 1 TYP. GENERAL DESCRIPTION
SAA4960
The SAA4960 is an adaptive alignment-free one chip comb filter compatible with PAL systems and provides high performance in Y/C separation.
MAX. 5.5 5.5 5.5 5.5 90 20 40 3.0 1.4 1 400 1.54 1.1 1.54 V V V V
UNIT
mA mA mA mA V V mV V V V
ORDERING INFORMATION TYPE NUMBER SAA4960 PACKAGE NAME DIP28 DESCRIPTION plastic dual in-line package; 28 leads (600 mil) VERSION SOT117-1
1996 Oct 15
2
1996 Oct 15
+5 V +5 V +5 V D A 100 nF A 100 nF 47 PLLGND AGND 9 7 11 8 21 22 5 24 26 27 VCCPLL OGND VCCO DGND REFBP REFDL VCCA VDDD 100 nF 100 F A 100 nF 100 nF 100 F A 100 F +5 V A 100 nF 100 F
handbook, full pagewidth
BLOCK DIAGRAM
Philips Semiconductors
D
A
HDET VDET LPFO1 HSEL SYSPAL CL3 STOPS DELAY COMPENSATION LPFO1 CVBSDL CONT1 HDET VDET BPF -1 CL3 LPFO1 YCOMB CL3 BPF BPF CONT1 CCOMB DELAY LINES S1 S2C CL3 CL3 BPF CONT1 COMB FILTER LPFO2 12 CO STOPS S2B CL3 14 YO CL3 CONT2 LPF CONTROL CONT1 CURRENT REFERENCE VOLTAGE REFERENCE
FSC 1
Integrated PAL comb filter
BYP 3
SSYN 6
FSCSW 13 S2A
CLOCK CONTROL
15 CVBSO
COMBENA 25
A
CSY 19
3
HSEL CL3 SYSPAL CL3 CL3 4 i.c. 16 i.c. 2 i.c. 28 i.c.
100 nF
SYNC SEPARATOR
Yext/CVBS 17
CLAMP
100 nF
+5 V
LPFI
CONT2
LPFION 18
n.c. 23
n.c. 20
Cext 10
BIAS
SAA4960
100 nF
MHA366
Remark: all switches in LOW position.
Preliminary specification
SAA4960
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
PINNING SYMBOL FSC i.c. BYP i.c. REFBP SSYN VCCA VCCO AGND Cext OGND CO FSCSW YO CVBSO i.c. Yext/CVBS LPFION CSY n.c. DGND VDDD n.c. REFDL COMBENA PLLGND VCCPLL i.c. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION subcarrier frequency input internally connected bypass mode forcing input internally connected decoupling capacitor for band-pass filter reference bypass definition input analog supply voltage analog supply voltage output buffer analog ground (signal reference) external chrominance input signal analog ground output buffer chrominance output signal fsc reference selection input luminance output signal uncombed CVBS output signal internally connected CVBS (VBS) input signal disable alias-filter storage capacitor not connected digital ground digital supply voltage not connected decoupling capacitor for delay lines COMB-mode output signal analog ground PLL analog supply voltage PLL internally connected Fig.2 Pin configuration.
SAA4960
handbook, halfpage
FSC i.c. BYP i.c. REFBP SSYN VCCA VCCO AGND
1 2 3 4 5 6 7
28 i.c. 27 VCCPLL 26 PLLGND 25 COMBENA 24 REFDL 23 n.c. 22 VDDD
SAA4960
8 9 21 DGND 20 n.c. 19 CSY 18 LPFION 17 Yext/CVBS 16 i.c. 15 CVBSO
MHA365
Cext 10 OGND 11 CO 12 FSCSW 13 YO 14
1996 Oct 15
4
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
FUNCTIONAL DESCRIPTION Functional requirements The PAL comb filter processes the video standards PAL B, G and H. PAL D and I signals can also be processed but with the drawback of a slightly reduced bandwidth. For SECAM and SVHS signals, the input signals can be bypassed to the output without processing by selecting the BYPASS-mode. A sync separation circuit is incorporated to generate control signals for the internal clock processing. With a sync compression of up to 12 dB the sync separator works properly (see Fig.4). The IC is controlled via four pins: 1. BYP forces the IC into the BYPASS-mode (comb filter function off) 2. SSYN defines whether the COMB-mode is entered synchronously or not and defines the polarity of the BYP pin 3. FSCSW selects the reference frequency fsc or 2 x fsc 4. LPFION enables the internal pre-filter. It is possible to select the following modes of operation: COMB-mode: Luminance and chrominance comb filter function active if BYPASS-mode not active. BYPASS-mode: Signal processing not active, all clocks inactive, Cext (pin 10) is bypassed to CO (pin 12) and Yext/CVBS (pin 17) is bypassed to YO (pin 14) and CVBSO (pin 15). This mode is forced via BYP (pin 3). If the stimulus of the mode is changed, the IC is following the new mode after the stabilization time given in Table 1. Table 1 Stabilization time after mode change MODE CHANGE COMB-mode to BYPASS-mode BYPASS-mode to COMB-mode MAXIMUM STABILIZATION TIME 1 line 1 field Pin description FSC (PIN 1)
SAA4960
Input for the reference frequency fsc (see note 2 of Chapter "Characteristics") or 2 x fsc. For SECAM standard signals the best signal performance in BYPASS-mode is achieved by switching the FSC input signal off externally. BYP (PIN 3) Input signal that controls the operation mode. A low-pass filter is added to the input for suppression of subcarrier frequencies. Thus applications are supported where the operation mode (COMB or BYPASS) is controlled by the DC-level of the FSC input signal at pin 1. For those applications the BYP input can be externally connected to FSC (pin 1). Depending on SSYN (pin 6) the function of BYP can be adapted to a certain application with respect to the polarity of the logic level and with respect to the behaviour when entering the COMB-mode. Dependent on SSYN the BYP input can be either inverted or non-inverted with the function as shown in Table 2: Table 2 SSYN LOW LOW HIGH HIGH Bypass function BYP LOW HIGH LOW HIGH SELECTED MODE COMB-mode BYPASS-mode BYPASS-mode COMB-mode
Dependent on SSYN the behaviour when entering the COMB-mode is different for the both selectable logic polarities while the BYPASS-mode is always entered asynchronously (immediately). Table 3 SSYN LOW HIGH Behaviour when entering the COMB-mode ENTERING COMB-MODE immediately if BYP = LOW synchronized by vertical pulse if BYP = HIGH
The mode change from BYPASS to COMB depends on SSYN (pin 6) and can be asynchronous or synchronous related to the vertical pulse. The mode change from COMB to BYPASS is always performed asynchronously.
The PLL and the clock processing are always stopped if the selected level for BYPASS is applied to BYP (independent of the vertical pulse).
1996 Oct 15
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
REFBP (PIN 5) Decoupling capacitor for the band-pass filter reference voltage. SSYN (PIN 6) Input signal that controls the function of BYP (pin 3). VCCA, VCCO, VDDD AND VCCPLL (PINS 7, 8, 22 AND 27) Supply voltages. AGND, OGND, DGND AND PLLGND (PINS 9, 11, 21 AND 26) Ground connection. AGND is used as signal reference for all analog input and output signals. Cext (PIN 10) Input for an external chrominance signal which is correlated to the external VBS signal. CO (PIN 12) Chrominance output signal. This output can be switched between the comb filtered chrominance from the CVBS signal and the external chrominance signal from the input Cext if the IC is forced into BYPASS-mode. Table 4 CO output signal CO OUTPUT SIGNAL comb filtered chrominance signal external chrominance signal of Cext input Yext/CVBS (PIN 17) Table 6 YO output signal
SAA4960
MODE COMB BYPASS
YO OUTPUT SIGNAL comb filtered luminance signal external CVBS signal of Yext/CVBS input
CVBSO (PIN 15) CVBS output signal directly from the input in BYPASS-mode or delayed by the signal processing time of 2 lines and an additional processing delay. Table 7 CVBSO output signal CVBSO OUTPUT SIGNAL delay compensated CVBS signal external CVBS signal of Yext/CVBS input
MODE COMB BYPASS
Input for the CVBS signal or for an external VBS signal. LPFION (PIN 18) Input signal to disable the internal pre-filter LPFI. Table 8 Pre-filter mode SELECTED MODE LPFI inactive LPFI active LPFI active
LPFION LOW HIGH Floating CSY (PIN 19)
MODE COMB BYPASS
FSCSW (PIN 13) Input signal to select between fsc or 2 x fsc as reference at the FSC input pin. Table 5 Reference frequency selection SELECTED REFERENCE 2 x fsc fsc
Sync top capacitor for the sync separator. REFDL (PIN 24) Decoupling capacitor for the delay line reference voltage. COMBENA (PIN 25) Output signal that indicates the current mode of operation. This output is forced to LOW if the comb filter is in BYPASS-mode. Table 9 Mode of operation SELECTED MODE BYPASS-mode; PLL and clock processing stopped COMB-mode
FSCSW HIGH LOW YO (PIN 14)
VBS output signal. This output can be switched between the comb filtered luminance signal (including synchronization) and the external (C)VBS signal from the input Yext/CVBS. In COMB-mode the output signal is delayed by 2 lines and by an additional processing delay. 1996 Oct 15 6
COMBENA LOW HIGH
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
Internal functional description SWITCHED CAPACITOR DELAY LINE Delays the CVBS input signal by 2 lines and 4 lines. Input signals for the delay lines are the CVBS signal, the clock CL3 (3 x fsc), the control signal HSEL and the standard selection signal SYSPAL. Output signals are the non-delayed, the 2-line delayed and the 4-line delayed CVBS signal. SWITCHED CAPACITOR BAND-PASS FILTERS (BPF) The comb filter input BPFs attenuate the low frequencies to guarantee a correct signal processing within the logical comb filter. The comb filter output BPF reduces the alias components that are the result of the non-linear signal processing within the logical comb filter. LOGICAL COMB FILTER Separates the chrominance from the band-pass filtered CVBS signal. COMPENSATION DELAY Compensates the internal processing time of the band-pass filters and the logical comb filter section. ADDER The comb filtered luminance output signal is obtained by adding the delayed CVBS signal and the inverted comb filtered chrominance signal. LOW-PASS FILTER INPUT (LPFI) Analog input low-pass filter to reduce the outband frequencies of EMC. The input low-pass filter is included in the signal path but it can be switched off via the input signal LPFION. LOW-PASS FILTER OUTPUT (LPFO1 AND LPFO2) Two different types of output low-pass filters (LPFO1 and LPFO2) are necessary to get equal signal delays within the luminance path and the chrominance path (important for good transient behaviour). The low-pass output filter type LPFO1 is used for the luminance output while LPFO2 is used for the chrominance output. The filters are analog 3rd order elliptic low-pass filters that convert the output signals from the time discrete to the time continuous domain (reconstruction filter). LPF CONTROL
SAA4960
Automatic tuning of the low-pass filters is achieved by adjusting the filter delays. The control information for all filters (CONT1 and CONT2) is derived from a built-in reference filter (LPFO1-type) that is part of a control loop. The control loop tunes the reference filter delay and thus all other filter delays to a time constant derived from the system clock CL3. CONTROL AND CLOCK PROCESSING (CLOCK CONTROL) The control and clock processing block (see Fig.7) consists of the sub-blocks PLL, the clock processing and the mode control. The PLL and the clock processing are released for operation if the input level at BYP selects the COMB-mode. Main tasks of the control and clock processing are: * Clock generation of system clock CL3 * Delay line start control * Mode control. The signal processing is based on a 3 x fsc system clock (CL3), that is generated by the clock processing from the fsc signal at FSC (pin 1) via a PLL. Because the subcarrier frequency divided by the line frequency results not in an integer value a clock phase correction of 180 is necessary every second line for PAL standards. The clock phase correction is controlled by the input signals horizontal sync. Additionally the delay line start is synchronized once a field to the input signals horizontal sync. The 25 Hz PAL offset is corrected in this way. The PLL provides a master clock MCK of 6 x fsc, which is locked to the subcarrier frequency at FSC (pin 1). The system clock CL3 (3 x fsc) is obtained from MCK by a divide-by-two circuit. The 180 phase shift is generated by stopping the divide-by-two circuit for one MCK clock cycle. The generated clock is a pseudo-line-locked clock that is referenced to fsc. The sync separator generates the necessary signals HDET and VDET indicating the line (H) and the field (V) sync periods. The current mode of operation (BYPASS or COMB) is external readable via COMBENA (pin 25).
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
The input signals of the control and clock processing (CLOCK CONTROL) are: HDET: analog horizontal pulse from sync separator VDET: analog vertical pulse from sync separator FSC: subcarrier frequency (fsc or 2 x fsc) FSCSW: reference frequency selection BYP: BYPASS control signal SSYN: vertical synchronous mode selection for BYP and polarity selection of BYP. The output signals are: CL3: system clock (3 x fsc) HSEL's: line start signals for the delay lines STOPS: forces the comb filter via the switches S2A, S2B and S2C into the BYPASS-mode (always asynchronous) or COMB-mode (synchronous or asynchronous with VINT; depending on SSYN) COMBENA: HIGH during COMB-mode; otherwise LOW. Table 10 Function of STOPS signal STOPS-STATE LOW HIGH SELECTED MODE COMB BYPASS SIGNAL SWITCH S2A Table 11 Function of signal switch S1 LPFION-STATE LOW HIGH Floating
SAA4960
DELAY LINE INPUT non-pre-filtered input signal Yext/CVBS pre-filtered input signal Yext/CVBS pre-filtered input signal Yext/CVBS
For the CVBSO output two signals can be selected via the signal switch S2A. Table 12 CVBSO output signal STOPS-STATE LOW HIGH CVBSO OUTPUT SIGNAL delayed input CVBSDL non-delayed input Yext/CVBS MODE COMB BYPASS
SIGNAL SWITCHES S2B AND S2C Two switches are included to bypass the comb filter signal processing. The input video signal Cext for the switch S2C is internally biased. For the YO output two signals can be selected via S2B. Table 13 YO output signal STOPS-STATE LOW HIGH YO OUTPUT SIGNAL YCOMB (combed luminance) input Yext/CVBS MODE COMB BYPASS
HORIZONTAL AND VERTICAL SYNC SEPARATOR A build-in sync separator circuit generates the HDET and VDET signals from the Yext/CVBS input signal. This circuit is still working properly at input signals with a 12 dB attenuated sync in a normal 700 mV black-to-white video signal (see Fig.4). CLAMP The black level clamping of the video input signal is performed by the sync separator stage. The clamping level is nearly adequate to the voltage at REFDL (pin 24). SIGNAL SWITCH S1 The switch is included to bypass the low-pass input filter. For the CVBS input of the delay line block two signals can be selected via the slow signal switch S1.
For the CO output two signals can be selected via S2C. Table 14 CO output signal STOPS-STATE LOW HIGH CO OUTPUT SIGNAL CCOMB (combed chrominance) input Cext MODE COMB BYPASS
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC V ICC IO Ptot Tamb Tstg Ves Note PARAMETER supply voltage input voltage protection threshold total supply current output current (CO, YO and CVBSO) output current (COMBENA) total power dissipation operating ambient temperature storage temperature electrostatic handling note 1 except pin 1 CONDITIONS - -0.3 - - - - 0 -25 MIN.
SAA4960
MAX. 6.5 155 15 10 900 70 +150 V VCC + 0.3 V
UNIT
mA mA mA mW C C
1. Human Body Model: C = 100 pF; R = 1.5 k; V = 2 kV; charge device model: C = 200 pF; R = 0 ; V = 300 V. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 31 UNIT K/W
1996 Oct 15
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
CHARACTERISTICS VDDD = VCCA = VCCO = VCCPLL = 5 V; Tamb = 25 C; input signal Yext/CVBS = 1 V (p-p) (0 dB); input signal C = 0.7 V (p-p) (0 dB); input signal FSC = 200 mV (p-p), sine wave, DC level = 2 V; input signal LPFION = 5 V; test signal: EBU colour bar 100/0/75/0 "CCIR471-1"; source impedance for Yext/CVBS, Cext = 75 decoupled with 100 nF; source impedance for FSC = 75 ; load impedance for CVBSO, YO, CO = 1 k and 20 pF in parallel; unless otherwise specified. SYMBOL Supply voltage VCCA VCCO VDDD VCCPLL FSC (pin 1) V1(p-p) input AC voltage (peak-to-peak value) input AC voltage is valid for sine wave square wave V1 C1 Ileak Z1 BYP (pin 3) VIH VIL Ileak C3 V5 SSYN (pin 6) VIH VIL Ileak C6 VCCA (pin 7) ICCA VCCO (pin 8) ICCO supply current - 70 90 mA analog supply current - 35 40 mA HIGH level input voltage LOW level input voltage input leakage current input capacitance 2.4 0 - - - 0.85 - - VCC 1.5 10 10 V V A pF HIGH level input voltage LOW level input voltage input leakage current input capacitance 2.4 0 - - - 0.85 - - VCC 1.5 10 10 V V A pF input DC level input capacitance input leakage current source impedance - 0.4 0 - - - - 0.5 - - - - - 0.6 5.3 10 10 800 - duty cycle V pF A 100 200 400 mV analog supply voltage (pin 7) analog supply voltage output buffer (pin 8) digital supply voltage (pin 22) analog supply voltage PLL (pin 27) note 1 note 1 note 1 note 1 4.75 4.75 4.75 4.75 5 5 5 5 5.5 5.5 5.5 5.5 V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
REFBP (pin 5) DC voltage 1.1 1.25 1.4 V
1996 Oct 15
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
SYMBOL Cext (pin 10) V10 R10 C10 Z10 CO (pin 12) V10/V12 V12 V12 R12 RL CL V17/V12
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
input voltage (AC coupled) input resistance input capacitance source impedance fsc 0.3fsc; note 2 1.25 V
- 500 - - -1 -400 - - 0.3 - see Fig.5 and note 3 283 x fH (283 - 43) x fH (283 + 35) x fH 26 20 20 - - - - 26 56 - - 0.95
0 700 - -
3 1000 10 1
dB k pF k
BYPASS-mode: CO/Cext DC offset voltage related to input DC jump when forcing into BYPASS-mode output resistance load resistance (to ground) load capacitance (to ground) suppression (comb depth)
0 0 100 10 - -
+1 +400 450 100 - 25
dB mV mV k pF
COMB-mode: transfer function C-path see Fig.8
30 24 24 - - - - 30 72 -60 - - - - - -
- - - -30 -50 -37 -30 - - -40 -60 -
dB dB dB dB dB dB dB dB dB dB dB
FPN
fixed pattern noise for divided clock frequencies referenced to 0.7 V (p-p)
0.75fsc fsc 1.5fsc 2fsc
cr S/N cr V12(p-p) Gd VIH VIL C13 Ileak
crosstalk suppression at vertical transients no-colour colour signal-to-noise ratio (0.7 V/Veff noise) crosstalk between different inputs FSC residue in BYPASS-mode related to 700 mV (p-p) differential gain
see Fig.3 unweighted; fsc 0.3fsc; note 2 0 to 5 MHz
FSCSW (pin 13) HIGH level input voltage LOW level input voltage input capacitance input leakage current 2 0 - - VCC 0.8 10 10 V V pF A
1996 Oct 15
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
SYMBOL YO (pin 14) V14/V17 V14 V14 R14 RL CL V17/V14
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BYPASS-mode: CO/Cext DC offset voltage related to input DC jump when forcing into BYPASS-mode output resistance load resistance (to ground) load capacitance (to ground) suppression (comb depth)
0 to 5 MHz
-1 -400 - - 0.3 -
0 0 200 10 - -
+1 +400 450 100 - 25
dB mV mV k pF
COMB-mode: transfer function Y-path see Fig.9
see Fig.6 and note 3 283.75 x fH 26 30 12 24 - - - - 30 72 -60 - - - - - -40 -30 -30 -20 - - -40 -60 - dB dB dB dB dB dB dB dB dB dB dB (283.75 - 43) x fH 10 (283.75 + 35) x fH 18
FPN
fixed pattern noise for divided clock frequencies referenced to 0.7 V (p-p) black-to-white
0.75fsc fsc 1.5fsc 2fsc see Fig.3 unweighted; 200 kHz to 5 MHz 0 to 5 MHz
- - - - 26 56 - - 0.95 -1 -400 - - 0.3 -
cr S/N cr V14(p-p) Gd V15/V17 V15 V15 R15 RL CL FPN
crosstalk suppression at vertical transients gray multi-burst signal-to-noise ratio (0.7 V/Veff noise) crosstalk between different inputs FSC residue in BYPASS-mode related to 700 mV (p-p) differential gain
CVBSO (pin 15) BYPASS-mode: CVBSO/CVBS DC offset voltage DC jump when forcing into BYPASS-mode output resistance load resistance (to ground) load capacitance (to ground) fixed pattern noise for divided clock frequencies referenced to 0.7 V (p-p) black-to-white 0.75fsc fsc 1.5fsc 2fsc S/N signal-to-noise ratio (0.7 V/Veff noise) unweighted; 200 kHz to 5 MHz 0 to 5 MHz 0 0 200 10 - - - - - - 72 +1 +400 450 100 - 25 -40 -30 -30 -20 - dB mV mV k pF dB dB dB dB dB COMB-mode: transfer function CVBS-path see Fig.9
- - - - 56
1996 Oct 15
12
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
SYMBOL cr V15(p-p) Gd Pd
PARAMETER crosstalk between different inputs FSC residue in BYPASS-mode related to 700 mV (p-p) differential gain differential phase
CONDITIONS 0 to 5 MHz - -
MIN. - - 2
TYP. -60
MAX. -40 -60 - 3
UNIT dB dB
0.95 - -3
deg
Yext/CVBS (pin 17) V17 input voltage (AC coupled) 12 dB sync attenuation possible; see Fig.4 0 +3 dB
I17 V17 Z17 VIH VIL I18 C18 CSY (pin 19) V19 VDDD (pin 22) IDDD V24 VOL VOH IOH
input current during sync pulse input current during active video DC voltage during black level source impedance
-10 - 1.1 -
-8.0 0.84 1.25 - - - 8 8 -
- 1.5 1.4 1
A A V k
LPFION (pin 18) HIGH level input voltage LOW level input voltage input current input capacitance 0.8 V 2.0 V 2 0 - - - VCC 0.8 20 20 10 V V A A pF
DC voltage
0 -
2.45
VCC
V
supply current
10
20
mA
REFDL (pin 24) DC voltage 1.1 1.25 1.4 V
COMBENA (pin 25) LOW level output voltage HIGH level output voltage HIGH level output current 2.4 V 3 mA 0.26 4 -55 - 0.4 - -24 0.55 VCC - V V A
VCCPLL (pin 27) I27 supply current V = V CCA - V DDD 300 mV V = V CCA - V CCO 300 mV V = V CCO - V DDD 300 mV All voltages are related to AGND. 2. Subcarrier frequency fsc = 4.43361875 MHz. 3. Line frequency fH = 15.625 kHz. 1.5 3 mA
Notes to the characteristics 1. V = V CCA - V CCPLL 300 mV V = V CCO - V CCPLL 300 mV V = V DDD - V CCPLL 300 mV
1996 Oct 15
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidthinput
line 1
line 2
line 3
line 4
line 5
line 6
line 7
line 8
output
vertical transient
MHA367
Fig.3 Vertical transmission by different video signals from line to line.
handbook, full pagewidth
1.0
(V)
0.45
0.3 0.225 0.15
0
MHA370
Fig.4 EBU colour bar 100/0/75/0 with 12 dB sync attenuation.
1996 Oct 15
14
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidth
U, V: PAL B, G, H, D, I fsc V U
Y
Y
(n - 1)fH
(n - 0.75)fH
(n - 0.25)fH
nfH
MHA368
Fig.5 Principle frequency response of a comb filtered PAL chrominance signal.
handbook, full pagewidth
U, V: PAL B, G, H, D, I fsc
Y
Y
V
U
(n - 1)fH
(n - 0.75)fH
(n - 0.25)fH
nfH
MHA369
Fig.6 Principle frequency response of a comb filtered PAL luminance signal.
1996 Oct 15
15
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidth
1
SSYN VINT
1 &
=1
BYP
&
1
COMBENA
STOPS
1
CL3 CL3 HDET CLOCK PROCESSING VDET 4 HSEL VINT
FSC PLL FSCSW
MCK
STOP
MHA371
Fig.7 Clock control.
1996 Oct 15
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Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
gain handbook, full pagewidth (dB) +1 0 -1 -3
-25 -30 0.4 0.66 0.85 1 1.12 1.35 2.0 2.26 frequency (fsc)
MHA372
2.7
Fig.8 Chrominance path: tolerance band with anti-alias filter.
gain handbook, full pagewidth (dB) +1 0 -1 -2 -3 -5
-32 0.7 1 1.12 1.5 2.26 frequency (fsc)
MHA373
2.7
Fig.9 Luminance and CVBSO path: tolerance band with anti-alias filter.
1996 Oct 15
17
1996 Oct 15
handbook, full pagewidth
FSC FSC 1 28 VCCPLL 2 VCCPLL 10 nF 100 nF 100 F VDDD i.c. VDDDS 33 H 1
Philips Semiconductors
75 i.c. 2 27 PLLGND COMBENA VCCO 10 nF 100 nF 100 F VCCA VCCA 7 22 VDDD VDDD 10 nF 100 nF VCCAS 33 H 1 100 F 2 100 nF 100 F 2
BYP 3 4 25 REFDL COMBENA VCCOS 33 H 1 26
Integrated PAL comb filter
i.c.
TEST AND APPLICATION INFORMATION
47 REFBP 5 24 n.c.
100 nF SSYN 6 23
VCCA VCCO 8 21 n.c. VCCPLL DGND
SAA4960
18
AGND 9 20 CSY 100 nF OGND 11 18 Yext/CVBS 100 nF FSCSW 13 CVBSO 10 k 16 i.c. 75 LPFION Cext 10 19 100 nF 10 nF CO 12 17 CVBS YO 14 15
VCCO
Cext
75
VCCPLLS 33 H 1 100 nF 100 F 2
MHA374
SVHS
4
SVHS-C
3
10 k
2
1
10 k
VDDD
SVHS-Y
Preliminary specification
SAA4960
Fig.10 Test circuit.
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidth
5.6 k
COMBENA BYP 25 Cext SVHS-C 10 SAA4960 SVHS-VBS TDA8540 CVBS1 SWITCH CVBS2 I2C-bus Yext/CVBS COMB FILTER 17 6 SSYN +5 V 13 3 1
FSC CO YO TDA9141 MSD
12
-(R - Y) -(B - Y)
14
15
CVBSO
TDA4665 BBDL
VB
FSCSW CVBSO I2C-bus
MHA375
Fig.11 Application diagram: SAA4960 with TDA9141.
handbook, full pagewidth
+5 V I2C-bus 3.3 k 1 k BC548 4.43 MHZ COMBENA BYP 25 Cext 3 1 12 SAA4960 CO YO CVBSO 15 6 SSYN I2C-bus +5 V 13 FSCSW I2C-bus
MHA376
PCF8574 I2C-I/O PORT
FSC
SVHS-C
10
TDA9160/62 MSD
-(R - Y) -(B - Y) VB TXT
SVHS-VBS TDA8540 CVBS1 SWITCH CVBS2 Yext/CVBS COMB FILTER 17
14
TDA4665 BBDL
Fig.12 Application diagram: SAA4960 with TDA9160/62.
1996 Oct 15
19
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidth
I2C-bus
PCF8574 I2C-I/O PORT IF input
BYP 3 Cext SVHS-C 10 SAA4960 SVHS-VBS TDA8540 CVBS1 SWITCH CVBSint I2C-bus Yext/CVBS COMB FILTER 17 6 SSYN 13 1
FSC CO YO TDA8366 MSD
12
R
14
G TDA4665 BBDL
15
CVBSO
B
FSCSW CVBSO I2C-bus
MHA377
Fig.13 Application diagram: SAA4960 with TDA8366.
handbook, full pagewidth
I2C-bus
PCF8574 I2C-I/O PORT 2 x FSC
BYP 3 Cext SVHS-C 10 SAA4960 SVHS-VBS TDA8540 CVBS1 SWITCH CVBS2 I2C-bus Yext/ CVBS 17 6 SSYN 13 COMB FILTER
FSC 1 12 CO
CHROMINANCE BANDPASS
TDA4655 MSD TDA4665 BBDL
-(R - Y) -(B - Y)
LUMINANCE TRAP 14 15 YO CVBSO VBS
CVBSO
MHA378
FSCSW +5 V
Remark: all switches in LOW position.
Fig.14 Application diagram: SAA4960 with TDA4655.
1996 Oct 15
20
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
PACKAGE OUTLINE
handbook, plastic dual in-line package; 28 leads (600 mil) DIP28: full pagewidth
SAA4960
SOT117-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 28 15 MH wM (e 1)
pin 1 index E
1
14
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.020 0.014 c 0.32 0.23 0.013 0.009 D (1) 36.0 35.0 1.41 1.34 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 1.7 0.067
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT117-1 REFERENCES IEC 051G05 JEDEC MO-015AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1996 Oct 15
21
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4960
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Oct 15
22
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
NOTES
SAA4960
1996 Oct 15
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp24
Date of release: 1996 Oct 15
Document order number:
9397 750 01366

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